To further increase the density of a semiconductor product and improve the performance of the semiconductor product by shortening a wiring length between circuits, a 2.5-dimensional stacking technology and a three-dimensional stacking technology for a semiconductor chip have been attracting attention. In the 2.5-dimensional stacking technology for a semiconductor chip, a plurality of semiconductor chips (dies) are loaded adjacent to one another on a silicon interposer. In the three-dimensional stacking technology for a semiconductor chip, a plurality of semiconductor chips are stacked, and the plurality of semiconductor chips are connected to one another by being each penetrated by a TSV (Through Silicon Via).
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[Patent document 2] Japanese Laid-open Patent Publication No. 2010-21306
[Patent document 3] Japanese Laid-open Patent Publication No. 2009-277334
[Patent document 4] Japanese Laid-open Patent Publication No. 2014-2826